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Software-Defined Radio8 min read

AD9361 + SoC-FPGA Architecture for Tactical Software-Defined Radios

A reference architecture for a 70 MHz–6 GHz software-defined radio built on a wide-tuning RF transceiver and an SoC-FPGA, with the trade-offs that matter for tactical comms and ISR cueing.

Why this combination

Two parts dominate the tactical SDR design space because they collapse what used to be a discrete-component RF chain into a single chip plus a fabric companion: the AD9361 wide-tuning RF transceiver from Analog Devices, and a Zynq-class SoC-FPGA from Xilinx/AMD.

The AD9361 integrates the receive and transmit chains — LNA, mixer, baseband filter, gain control, fractional-N synthesizer, ADC/DAC — into a single die. It tunes from 70 MHz to 6 GHz and supports baseband bandwidths from 200 kHz to 56 MHz. From a system engineer's perspective, an entire RF cassette collapses into one chip plus a balun and a PA. From an SWaP perspective, it's the difference between a radio that fits a man-pack and one that does not.

The Zynq companion gives you the rest of the radio: a programmable-logic side that handles the high-rate baseband DSP (digital down-conversion, channel filtering, demodulation, framing), and a processing-system side running Linux for protocol stack, key management, and operator interface.

Block diagram

   ┌────────────────┐     LVDS / I-Q     ┌──────────────────────┐
   │   AD9361 RFIC   │ ←─────────────────→ │   Zynq PL (fabric)   │
   │  70 MHz – 6 GHz │                    │  - DDC / DUC chain    │
   │  ADC/DAC + Synth│ ←── SPI config ──→ │  - Channel filters    │
   └────────────────┘                    │  - Symbol sync         │
            ↑↓ RF                         │  - Framer / deframer   │
            ┌──────────┐                  └──────────────────────┘
            │ PA / LNA │                              ↑↓ AXI4
            │  + duplex│                  ┌──────────────────────┐
            └──────────┘                  │   Zynq PS (Linux)    │
                                          │  - Waveform manager   │
                                          │  - Key / crypto chain │
                                          │  - Operator I/F        │
                                          └──────────────────────┘

What the architecture buys you

Waveform agility. Because the entire RF front-end is parameterized through SPI registers and the baseband DSP lives in fabric, switching between waveforms (narrowband VHF voice, wideband mesh, FH datalink) is a configuration change, not a hardware change. The same physical radio can be field-reprovisioned for a different mission.

Frequency-hop spread spectrum. The fractional-N synthesizer in the AD9361 can retune in under 1 ms. Combined with a fabric-side hop sequencer, this supports FHSS waveforms in the 1–10 kHz hop range, which is the operating space of most modern tactical hop schemes.

Cooperative MIMO and beamforming-lite. Two AD9361 devices paired with a Zynq give four coherent RX channels, which is enough for null-steering against a known interferer or for direction-finding within a hemisphere. Full digital beamforming requires more channels, but two-element null-steering is a useful first step that fits in a man-pack.

Where it doesn't fit

This architecture is not the right choice for:

  • Very wideband applications — anything that wants >100 MHz of instantaneous bandwidth is better served by a different transceiver class (e.g., the Analog Devices RFSoC-class parts, which integrate ADCs of >2 GSPS directly on the FPGA die).
  • Sub-MHz HF work — the AD9361's specified low-end of 70 MHz means HF requires an external down-converter or a different RFIC entirely.
  • High-power transmit — the chip drives a few hundred milliwatts. Anything beyond squad-level range needs an external PA, which then drives thermal and antenna-isolation design.

Implementation realities

Three subtleties bite teams who haven't built this before:

  1. Calibration is not free. The AD9361 does a remarkable job of automatic gain control, but its DC-offset and quadrature calibration sequences take 10–50 ms after retune. Frequency-hopping waveforms must either pre-stage calibration data per channel or accept blanking at the start of each dwell.
  2. PS-to-PL coherency matters. The control plane (Linux on PS) wants to set RF parameters from userspace. The data plane (fabric) is reading I-Q samples at sustained 60 Msps. A naïve AXI4 design will create back-pressure that shows up as occasional sample drops. Either lock the configuration channel to be host-driven only during gaps in the data plane, or use a dedicated low-rate config bus.
  3. Key material isolation. The Zynq PS is a general-purpose Linux platform and should not be considered a HAIPE-class enclave. If the radio carries classified traffic, the cryptographic boundary must sit outside the PS — typically in a separate hardware security module, or in a fabric-side crypto core whose key store is fused at provisioning time.

Why we care

Sustainment workflows in contested environments live or die on intermittent comms. A sustainment platform that "fails silent" when the radio link drops is worse than one that degrades gracefully and resyncs when the link returns. Understanding how the radio actually behaves — calibration latency, retune time, FHSS guard intervals — lets us design our message protocols against the real envelope of the link, not the brochure version.