Camera Integration at the SoC-FPGA Boundary: MIPI CSI-2 vs Parallel for Mission Optics

Why the interface matters

A vision-equipped compute node has three things on the optical board: an image sensor, a lens, and an interface to the processor. The lens and sensor get most of the engineering attention because they're visible in the spec sheet ("4K @ 60 fps with f/1.8 optics"). The interface gets the rest of the design's reliability profile.

Three interface families dominate field-deployable vision systems:

• Parallel digital video — 8 to 16 bits of pixel data plus pixel clock, hsync, vsync. Old, simple, robust.
• MIPI CSI-2 — the standard for modern mobile-derived sensors. Differential serial links over 1, 2, or 4 lanes.
• Sub-LVDS / HD-SDI / coaxial video — for sensors that need to be far from the processor (industrial machine vision, automotive camera-over-coax).

For a sensor mounted within a few centimeters of a Zynq-class SoC-FPGA — the typical configuration for a UAS payload, a vehicle sensor pod, or an inspection robot — the choice is between parallel and MIPI.

Parallel: robust, slow, awkward

Parallel digital video is the interface every old sensor used. Its strengths:

• Easy to verify with a scope. Every signal is single-ended digital. Bringing up a parallel sensor with a logic analyzer is a 30-minute exercise.
• No PHY required. The signals go directly into FPGA pins. No serializer, no deserializer, no clock recovery, no specialized FPGA primitives.
• Tolerant of small layout mistakes. A parallel bus that's slightly skewed still works; the system tolerates errors on the order of a pixel clock period.

Its weaknesses:

• Pin count. 16 bits of pixel data + 4 timing signals = 20 pins, which dominates the FPGA pin budget for what is otherwise a modest peripheral.
• Limited resolution-frame rate product. Above roughly 100 megapixels per second (a 1080p30 or 720p60 sensor), parallel signal integrity becomes hard. At 4K30 (250 megapixels per second) it's effectively unworkable.
• EMI. A 100 MHz parallel bus radiates. In an enclosure with sensitive RF circuitry, the parallel video interface is often the dominant EMI source.

Parallel is the right answer for legacy sensors, low-resolution applications, and short-pin-budget designs where the FPGA pin count is the binding constraint.

MIPI CSI-2: modern, dense, demanding

MIPI CSI-2 is the standard for current-generation image sensors. Its strengths:

• Pin efficiency. A 4-lane CSI-2 link carries 4K60 video on 10 pins (4 differential pairs + 1 differential clock).
• EMI behavior. Differential signaling at multi-gigabit rates radiates much less than wide parallel buses. The CSI-2 bus is usually invisible in EMI measurements.
• Standard timing model. All CSI-2 sensors look mostly the same to the FPGA's MIPI receiver. Switching between sensor parts is a configuration change, not a re-layout.

Its weaknesses:

• Layout is unforgiving. CSI-2 lanes must be length-matched within tens of mils, impedance-controlled to 100 Ω differential, and routed with no via discontinuities. A mistake at PCB layout invalidates the design.
• PHY required. The FPGA needs either dedicated MIPI receiver hardware or a soft MIPI receiver core that consumes a fair amount of fabric. The latter is bandwidth-limited.
• Verification requires a CSI-2 protocol analyzer. Bringing up a MIPI link with a generic logic analyzer is not realistic. The tooling investment is real.

CSI-2 is the right answer for any modern application that has access to dedicated MIPI hardware in the FPGA and the layout discipline to do it right.

Practical mitigation: SerDes bridges

A common pattern in vehicle and aircraft vision systems is to put a SerDes bridge between the sensor and the processor. The sensor connects via its native interface (parallel or CSI-2) to a serializer chip; the serializer drives a coax or twinax cable to a deserializer chip on the processor board; the deserializer presents the sensor's native interface to the FPGA.

This buys:

• Long sensor-to-processor distances. SerDes bridges run reliably over multiple meters of cable, which is the difference between mounting the sensor in the payload bay and mounting it on the airframe.
• EMI containment. The coax cable shields the link from external interference and contains its emissions.

The cost is two more chips in the BOM and the additional latency of the SerDes (typically 1–2 line periods). For most applications that latency is invisible.

Sustainment relevance

The architectural choice of camera interface affects whether a sensor stream can be added to a sustainment workflow without re-spinning a circuit board. Standard CSI-2 sensors swapped through a fixed SerDes bridge let an operator change the optical front end (different focal length, different spectrum, different sensitivity) without involving engineering. That deployment flexibility is a sustainment property in itself — the system stays useful as the mission and the threat environment change.